CERBERO Toolchain

The CERBERO Toolchain

To support the design and management of self-adaptive CPS, CERBERO offers a toolchain that operates at different levels of abstraction, from the computation level to the System level, delivering also user-level features (i.e. requirements and model verification). CERBERO tools offer support at design-time, for the design, verification and deployment of self-adaptive CPS, and at run-time for providing self-aware smart system management.
In order to ease the integration of different tools in a unique toolchain, CERBERO also provides the CERBERO Interoperability Framework (CIF), which enables the integration of some of developed tools.

Design–Time Support Run-Time Support


Name Support Description
SAGE Design-Time The SAGE Verification Suite leverages on formal methods and provides two tools; ReqV, to automatically check consistency of a set of requirements provided by the user and Hydra, to perform automated synthesis of high-level policies.
DynAA Design-Time
Dynaa is based on discrete-component models to find optimal solutions by means of model simulations. At run-time, Dynaa can be used to explore different solutions, interacting with signals that come from the system and the environment.
MECA Run-Time MECA improves the resilience of human-machine teams by providing system, environmental and human monitoring and diagnosis, and high-level decision support in cases of unforeseen conditions and events.
AOW Design-Time AOW works at system level to solve large scale hybrid optimization problems to return frontier of Pareto optimal solutions.
PREESM Design-Time PREESM enables parallel-application development with design-time prediction, as well as code generation and re-use capabilities.
SPIDER Run-Time SPIDER performs dynamic mapping and scheduling of reconfigurable dataflow applications on parallel heterogeneous architectures.
PAPIFY Design-Time
PAPIFY provides monitoring capabilities by means of an event library aimed at generalizing the Performance API (PAPI) for heterogeneous architectures. At run-time, PAPIFY provides a large set of execution monitors to enrich SPIDER scheduling.
MDC Design-Time
MDC tool is an automated dataflow-to-hardware framework for the generation and system integration of CGR accelerators.
ARTICo3 Design-Time
ARTICo3 exploits a DPR-enabled multi-accelerator computing scheme, to provide scalable parallelism. It also provides an automated toolchain to go from the user-defined application down to the system implementation.
JIT Design-Time
JIT hardware composition refers to the ability to implement, at run-time, hardware accelerators on FPGAs without a presynthesized design. IMPRESS, belonging to the JIT HW design suite, is a TCL script-based tool for the automated generation of relocatable partial bitstreams under Vivado.