Francesco Regazzoni

He is a senior researcher. He obtained his PhD from USI in 2009, and his MSc in Computer Engineering from Politecnico di Milano. He is work package leader of the SAFECrypto project (H2020 ICT644729) and was actively involved in Swiss National Foundation, Nanotera framework and Swiss Innovation projects; he was invited speaker at the special session Design methodologies for securing cyber-physical systems” held at the E Week conference in 2015. He has published more than 50 of papers on design automation for physical security, countermeasure against physical attacks, and design of optimized hardware and software for security. He is serving or served as TPC member or reviewer for a number of major security and design automation conferences including CHES, HOST, and DATE, and CODES and ICCAD.

Christian Pilato

He is a postdoctoral researcher at the ALaRI institute of Università della Svizzera italiana (USI). Dr. Pilato received the M.Sc. degree in Computer Engineering (2007) and the Ph.D. degree in Information Technology (2011), both from Politecnico di Milano. He was research assistant at Politecnico di Milano until 2013 and postdoctoral research scientist at Columbia University until 2016. Dr. Pilato has been visiting researcher at NanGate, Chalmers University of Technology, and Delft University of Technology. Dr. Pilato’s research interests focus on system-on-chip architectures, hardware accelerators, and high-performance computing. In particular, he developed solutions and CAD tools for the optimization of memory accesses during the high-level synthesis of hardware accelerators to process massive data sets with energy-efficient high performance. He has actively participated to several projects sponsored by European Union (hArtes, Synaptic, FASTER) and a research center (C-FAR) supported by Semiconductor Research Corporation and DARPA.